Computer Architecture - 99 Academic Year

計算機架構 - 99學年度

本課程是由 國立陽明交通大學資訊工程學系 提供。

Computer Architecture is one of the few fundamental subjects that a computer scientist must master. It describes how a computer system should be designed, from the user’s and the system view. It differs from the undergraduate course Computer Organization in that, this course tells you not only how current computers are designed, but also the future directions in accordance with technological changes, plus many design techniques in depth.

 

課程用書:

    • John L. Hennessy & David A. Patterson, Computer Architecture: A Quantitative Approach, 4th ed., 2007, Morgan Kaufmann.
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授課教師 資訊工程學系 單智君老師
課程學分 3學分
授課年度 99學年度
授課對象 碩士班學生
預備知識 Computer Organization (Undergraduate course)
課程提供 課程影音   課程綱要   課程行事曆  

週次課程內容課程影音課程下載
課程介紹線上觀看MP4下載
第一章 Fundamentals of Computer Design (1/3)
1-1 Introduction
1-2 Classes of Computers
1-3 Defining Computer Architecture
1-4 Trends in Technology
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第一章 Fundamentals of Computer Design (2/3)
1-5 Trends in Power in Integrated Circuits
1-6 Trends in Cost
1-7 Dependability
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第一章 Fundamentals of Computer Design (3/3)
1-7 Dependability
1-8 Measuring,Reporting and Summazing
1-9 Quantitative Principles of Computer Design
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Appendix B Instruction Set Principles and Examples (1/4)
B-1 Introduction
B-2 Classifying Instruction Set Architectures
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Appendix B Instruction Set Principles and Examples (2/4)
B-2 Classifying Instruction Set Architectures
B-3 Memory Addressing
B-4 Type and Size of Operands
B-5 Operations in the Instruction Set
B-6 Instructions for Control Flow
B-7 Encoding an Instruction
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Appendix B Instruction Set Principles and Examples (3/4)
B-8 Crosscutting Issues:The Role of Compilers
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Appendix B Instruction Set Principles and Examples (4/4)
B-9 Putting It All Together:The MIPS Architecture
Appendix A Pipelining: Basic and Intermediate Concepts (1/7)
A-1 Introduction
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
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Appendix A Pipelining: Basic and Intermediate Concepts (2/7)
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
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Appendix A Pipelining: Basic and Intermediate Concepts (3/7)
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
A-3 How Is Pipelining Implemented?
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Appendix A Pipelining: Basic and Intermediate Concepts (4/7)
A-4 What Makes Pipelining Hard to Implement?
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Appendix A Pipelining: Basic and Intermediate Concepts (5/7)
A-5 Extending the MIPS Pipeline to Handle Multicycle Operations
A-6 Putting It All Together:The MIPS R4000 Pipeline
A-7 Crosscutting Issues
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Appendix A Pipelining: Basic and Intermediate Concepts (6/7)
A-7 Crosscutting Issues
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Appendix A Pipelining: Basic and Intermediate Concepts (7/7)
A-7 Crosscutting Issues
第二章 Instruction Level Parallelism and Its Exploitation (1/7)
2-1 Instruction-Level Parallelism: Concepts and Challenges
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第二章 Instruction Level Parallelism and Its Exploitation (2/7)
2-1 Instruction-Level Parallelism: Concepts and Challenges
2-2 Basic Compiler Techniques for Exposing ILP
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第二章 Instruction Level Parallelism and Its Exploitation (3/7)
2-2 Basic Compiler Techniques for Exposing ILP
2-3 Reducing Branch Costs with Prediction
2-4 Overcoming Data Hazards with Dynamic Scheduling
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第二章 Instruction Level Parallelism and Its Exploitation (4/7)
2-4 Overcoming Data Hazards with Dynamic Scheduling
2-5 Dynamic Scheduling: Examples and the Algorithm
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第二章 Instruction Level Parallelism and Its Exploitation (5/7)
2-6 Hardware-Based Speculation
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第二章 Instruction Level Parallelism and Its Exploitation (6/7)
2-7 Exploiting ILP using Multiple Issue and Static Scheduling
2-8 Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
2-9 Advanced Techniques for Instruction Delivery and Sp
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第二章 Instruction Level Parallelism and Its Exploitation (7/7)
2-9 Advanced Techniques for Instruction Delivery and Speculation
第三章 Limits on Instruction-Level Parallelism (1/3)
3-1 Introduction
3-2 Studies of the Limitations of ILP
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第三章 Limits on Instruction-Level Parallelism (2/3)
3-3 Limitations on ILP for Realizable Processors
3-4 Crosscutting Issues: Hardware vs Software Speculation
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
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第三章 Limits on Instruction-Level Parallelism (3/3)
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
Appendix C Review of Memory Hierarchy (1/3)
C-1 Introduction
C-2 Cache Performance
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Appendix C Review of Memory Hierarchy (2/3)
C-3 Six Basic Cache Optimizations
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Appendix C Review of Memory Hierarchy (3/3)
C-3 Six Basic Cache Optimizations
C-4 Virtual Memory
C-5 Protection and Examples of Virtual Memory
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第五章 Memory Hierarchy Design (1/3)
5-2 Eleven Advanced Optimizations of Cache Performance
5-3 Memory Technology and Optimizations
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第五章 Memory Hierarchy Design (2/3)
5-1 Introduction
5-2 Eleven Advanced Optimizations of Cache Performance
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第五章 Memory Hierarchy Design (3/3)
5-3 Memory Technology and Optimizations
5-4 Protection: Virtual Memory and Virtual Machines
第四章 Multiprocessors and Thread-Level Parallelism (1/3)
4-1 Introduction
4-2 Symmetric Shared-Memory Architectures
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第四章 Multiprocessors and Thread-Level Parallelism (2/3)
4-2 Symmetric Shared-Memory Architectures
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第四章 Multiprocessors and Thread-Level Parallelism (3/3)
4-3 Performance of Symmetric Shared-Memory Multiprocessors
4-4 Distributed Shared Memory and Directory-Based Coherence
4-5 Synchronization: The Basics
4-6 Models of Memory Consistency: An Introduction
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課程目標

Computer Architecture is one of the few fundamental subjects that a computer scientist must master. It describes how a computer system should be designed, from the user’s and the system view. It differs from the undergraduate course Computer Organization in that, this course tells you not only how current computers are designed, but also the future directions in accordance with technological changes, plus many design techniques in depth.

 

課程章節

章節 章節內容
Fundamentals of Computer Design (Ch1)Introduction
Classes of Computers
Defining Computer Architecture
Trends in Technology
Trends in Power in Integrated Circuits
Trends in Cost
Dependability
Measuring, Reporting, and Summazing
Performance
Quantitative Principles of Computer Design
Instruction Set Principles and Examples (App. B)Introduction
Classifying Instruction Set Architectures
Memory Addressing
Type and Size of Operands
Operations in the Instruction Set
Instructions for Control Flow
Encoding an Instruction Set
Pipelining: Basic and Intermediate Concepts (App. A) Introduction
The Major Hurdle of Pipelining—Pipeline Hazards
How Is Pipelining Implemented?
What Makes Pipelining Hard to Implement?
Extending the MIPS Pipeline to Handle Multicycle Operations
Instruction Level Parallelism and Its Exploitation (Ch2)Instruction-Level Parallelism: Concepts and Challenges
Basic Compiler Techniques for Exposing ILP
Reducing Branch Costs with Prediction
Overcoming Data Hazards with
Dynamic Scheduling Dynamic Scheduling: Examples and the Algorithm
Hardware-Based Speculation
Exploiting ILP using Multiple Issue and Static Scheduling
Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
Advanced Techniques for Instruction Delivery and Speculation
Limits on Instruction-Level Parallelism (Ch3)Instruction-Level Parallelism: Concepts and Challenges
Basic Compiler Techniques for Exposing ILP
Reducing Branch Costs with Prediction
Overcoming Data Hazards with Dynamic Scheduling
Dynamic Scheduling: Examples and the Algorithm
Hardware-Based Speculation
Exploiting ILP using Multiple Issue and Static Scheduling Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
Advanced Techniques for Instruction Delivery and Speculation
Review of Memory Hierarchy (App. C) Introduction
Cache Performance
Six Basic Cache Optimizations
Virtual Memory
Protection and Examples of Virtual Memor
Memory Hierarchy Design (Ch5)Introduction
Eleven Advanced Optimizations of Cache Performance
Memory Technology and Optimizations
Protection: Virtual Memory and Virtual Machines
Multiprocessors and Thread-Level Parallelism (Ch4)Introduction
Symmetric Shared-Memory Architectures
Performance of Symmetric Shared-Memory Multiprocessors
Distributed Shared Memory and Directory-Based Coherence
Synchronization: The Basics
Models of Memory Consistency: An Introduction

 

課程書目

  • John L. Hennessy & David A. Patterson, Computer Architecture: A Quantitative Approach, 4th ed., 2007, Morgan Kaufmann.

 

參考資料

  • John L. Hennessy & David A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., 2003.

    Class notes of Prof. D. Culler & D. Patterson, UCB.

    Class notes of Prof. C. Chen & H.R. Ke, NCTU

 

評分標準

項目百分比
課堂參與與討論 
作業與小考20-40%
期中與期末考60-80%

本課程行事曆提供課程進度與考試資訊參考。

學期週次
上課日期
參考課程進度

第一週

02/22 02/25
  • Fundamentals of Computer Design
第二週03/01 03/04
  • Fundamentals of Computer Design
第三週03/08 03/11
  • Instruction Set Principles and Examples
第四週03/15 03/18
  • Pipelining: Basic and Intermediate Concepts
第五週03/22 03/25
  • Pipelining: Basic and Intermediate Concepts
第六週03/29 04/01
  • Pipelining: Basic and Intermediate Concepts
第七週04/05 04/08
  • Instruction Level Parallelism and Its Exploitation
第八週04/12 04/15
  • Instruction Level Parallelism and Its Exploitation
第九週04/19 04/22
  • Midterm Exam
第十週04/26 04/29
  • Limits on Instruction-Level Parallelism
第十一週05/03 05/06
  • Limits on Instruction-Level Parallelism
    Multiprocessors and Thread-Level Parallelism
第十二週05/10 05/13
  • Multiprocessors and Thread-Level Parallelism
第十三週05/17 05/20
  • Multiprocessors and Thread-Level Parallelism 
第十四週05/24 05/27
  • Review of Memory Hierarchy
第十五週05/31 06/03
  • Review of Memory Hierarchy
第十六週06/07 06/10
  • Memory Hierarchy Design
第十七週06/14 06/17
  • Memory Hierarchy Design
第十八週06/21 06/24
  • Final Exam