第二章 Instruction Level Parallelism and Its Exploitation (4/7), 2-4 Overcoming Data Hazards with Dynamic Scheduling, 2-5 Dynamic Scheduling: Examples and the Algorithm

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第一章 Fundamentals of Computer Design (1/3)
1-1 Introduction
1-2 Classes of Computers
1-3 Defining Computer Architecture
1-4 Trends in Technology
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第一章 Fundamentals of Computer Design (2/3)
1-5 Trends in Power in Integrated Circuits
1-6 Trends in Cost
1-7 Dependability
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第一章 Fundamentals of Computer Design (3/3)
1-7 Dependability
1-8 Measuring,Reporting and Summazing
1-9 Quantitative Principles of Computer Design
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Appendix B Instruction Set Principles and Examples (1/4)
B-1 Introduction
B-2 Classifying Instruction Set Architectures
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Appendix B Instruction Set Principles and Examples (2/4)
B-2 Classifying Instruction Set Architectures
B-3 Memory Addressing
B-4 Type and Size of Operands
B-5 Operations in the Instruction Set
B-6 Instructions for Control Flow
B-7 Encoding an Instruction
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Appendix B Instruction Set Principles and Examples (3/4)
B-8 Crosscutting Issues:The Role of Compilers
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Appendix B Instruction Set Principles and Examples (4/4)
B-9 Putting It All Together:The MIPS Architecture
Appendix A Pipelining: Basic and Intermediate Concepts (1/7)
A-1 Introduction
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
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Appendix A Pipelining: Basic and Intermediate Concepts (2/7)
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
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Appendix A Pipelining: Basic and Intermediate Concepts (3/7)
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
A-3 How Is Pipelining Implemented?
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Appendix A Pipelining: Basic and Intermediate Concepts (4/7)
A-4 What Makes Pipelining Hard to Implement?
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Appendix A Pipelining: Basic and Intermediate Concepts (5/7)
A-5 Extending the MIPS Pipeline to Handle Multicycle Operations
A-6 Putting It All Together:The MIPS R4000 Pipeline
A-7 Crosscutting Issues
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Appendix A Pipelining: Basic and Intermediate Concepts (6/7)
A-7 Crosscutting Issues
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Appendix A Pipelining: Basic and Intermediate Concepts (7/7)
A-7 Crosscutting Issues
第二章 Instruction Level Parallelism and Its Exploitation (1/7)
2-1 Instruction-Level Parallelism: Concepts and Challenges
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第二章 Instruction Level Parallelism and Its Exploitation (2/7)
2-1 Instruction-Level Parallelism: Concepts and Challenges
2-2 Basic Compiler Techniques for Exposing ILP
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第二章 Instruction Level Parallelism and Its Exploitation (3/7)
2-2 Basic Compiler Techniques for Exposing ILP
2-3 Reducing Branch Costs with Prediction
2-4 Overcoming Data Hazards with Dynamic Scheduling
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第二章 Instruction Level Parallelism and Its Exploitation (4/7)
2-4 Overcoming Data Hazards with Dynamic Scheduling
2-5 Dynamic Scheduling: Examples and the Algorithm
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第二章 Instruction Level Parallelism and Its Exploitation (5/7)
2-6 Hardware-Based Speculation
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第二章 Instruction Level Parallelism and Its Exploitation (6/7)
2-7 Exploiting ILP using Multiple Issue and Static Scheduling
2-8 Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
2-9 Advanced Techniques for Instruction Delivery and Sp
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第二章 Instruction Level Parallelism and Its Exploitation (7/7)
2-9 Advanced Techniques for Instruction Delivery and Speculation
第三章 Limits on Instruction-Level Parallelism (1/3)
3-1 Introduction
3-2 Studies of the Limitations of ILP
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第三章 Limits on Instruction-Level Parallelism (2/3)
3-3 Limitations on ILP for Realizable Processors
3-4 Crosscutting Issues: Hardware vs Software Speculation
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
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第三章 Limits on Instruction-Level Parallelism (3/3)
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
Appendix C Review of Memory Hierarchy (1/3)
C-1 Introduction
C-2 Cache Performance
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Appendix C Review of Memory Hierarchy (2/3)
C-3 Six Basic Cache Optimizations
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Appendix C Review of Memory Hierarchy (3/3)
C-3 Six Basic Cache Optimizations
C-4 Virtual Memory
C-5 Protection and Examples of Virtual Memory
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第五章 Memory Hierarchy Design (1/3)
5-2 Eleven Advanced Optimizations of Cache Performance
5-3 Memory Technology and Optimizations
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第五章 Memory Hierarchy Design (2/3)
5-1 Introduction
5-2 Eleven Advanced Optimizations of Cache Performance
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第五章 Memory Hierarchy Design (3/3)
5-3 Memory Technology and Optimizations
5-4 Protection: Virtual Memory and Virtual Machines
第四章 Multiprocessors and Thread-Level Parallelism (1/3)
4-1 Introduction
4-2 Symmetric Shared-Memory Architectures
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第四章 Multiprocessors and Thread-Level Parallelism (2/3)
4-2 Symmetric Shared-Memory Architectures
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第四章 Multiprocessors and Thread-Level Parallelism (3/3)
4-3 Performance of Symmetric Shared-Memory Multiprocessors
4-4 Distributed Shared Memory and Directory-Based Coherence
4-5 Synchronization: The Basics
4-6 Models of Memory Consistency: An Introduction
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