Appendix B Instruction Set Principles and Examples (2/4)
B-2 Classifying Instruction Set Architectures
B-3 Memory Addressing
B-4 Type and Size of Operands
B-5 Operations in the Instruction Set
B-6 Instructions for Control Flow
B-7 Encoding an Instruction
Appendix B Instruction Set Principles and Examples (4/4)
B-9 Putting It All Together:The MIPS Architecture
Appendix A Pipelining: Basic and Intermediate Concepts (1/7)
A-1 Introduction
A-2 The Major Hurdle of Pipelining—Pipeline Hazards
Appendix A Pipelining: Basic and Intermediate Concepts (5/7)
A-5 Extending the MIPS Pipeline to Handle Multicycle Operations
A-6 Putting It All Together:The MIPS R4000 Pipeline
A-7 Crosscutting Issues
Appendix A Pipelining: Basic and Intermediate Concepts (7/7)
A-7 Crosscutting Issues
第二章 Instruction Level Parallelism and Its Exploitation (1/7)
2-1 Instruction-Level Parallelism: Concepts and Challenges
第二章 Instruction Level Parallelism and Its Exploitation (3/7)
2-2 Basic Compiler Techniques for Exposing ILP
2-3 Reducing Branch Costs with Prediction
2-4 Overcoming Data Hazards with Dynamic Scheduling
第二章 Instruction Level Parallelism and Its Exploitation (4/7)
2-4 Overcoming Data Hazards with Dynamic Scheduling
2-5 Dynamic Scheduling: Examples and the Algorithm
第二章 Instruction Level Parallelism and Its Exploitation (6/7)
2-7 Exploiting ILP using Multiple Issue and Static Scheduling
2-8 Exploiting ILP using Dynamic Scheduling, Multiple Issue, and Speculation
2-9 Advanced Techniques for Instruction Delivery and Sp
第二章 Instruction Level Parallelism and Its Exploitation (7/7)
2-9 Advanced Techniques for Instruction Delivery and Speculation
第三章 Limits on Instruction-Level Parallelism (1/3)
3-1 Introduction
3-2 Studies of the Limitations of ILP
第三章 Limits on Instruction-Level Parallelism (2/3)
3-3 Limitations on ILP for Realizable Processors
3-4 Crosscutting Issues: Hardware vs Software Speculation
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
第三章 Limits on Instruction-Level Parallelism (3/3)
3-5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
Appendix C Review of Memory Hierarchy (1/3)
C-1 Introduction
C-2 Cache Performance
第四章 Multiprocessors and Thread-Level Parallelism (3/3)
4-3 Performance of Symmetric Shared-Memory Multiprocessors
4-4 Distributed Shared Memory and Directory-Based Coherence
4-5 Synchronization: The Basics
4-6 Models of Memory Consistency: An Introduction
